ESSI Data and Control Signals
transmitted, the STD signal does not assume a high-impedance state. The STD signal can be
programmed as a GPIO signal ( P5 ) when the ESSI STD function is not in use.
7.2.2 Serial Receive Data Signal (SRD)
SRD receives
serial data and transfers the data to the receive shift register. SRD can be
programmed as a GPIO signal ( P4 ) when the SRD function is not in use.
7.2.3 Serial Clock (SCK)
SCK is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The signal is
a clock input or output used by all the enabled transmitters and receivers in Synchronous modes
or by all the enabled transmitters in Asynchronous modes. See Table 7-1 for details. SCK can be
programmed as a GPIO signal ( P3 ) when not used as the ESSI clock.
Table 7-1. ESSI Clock Sources
SYN
SCKD
SCD0
RX Clock Source
RX Clock
Out
TX Clock Source
TX Clock Out
Asynchronous
0
0
0
0
0
0
1
1
0
1
0
1
EXT, SC0
INT
EXT, SC0
INT
SC0
SC0
EXT, SCK
EXT, SCK
INT
INT
SCK
SCK
Synchronous
1
1
0
1
0/1
0/1
EXT, SCK
INT
SCK
EXT, SCK
INT
SCK
Note:
Although an external serial clock can be independent of and asynchronous to the DSP
system clock, the external ESSI clock frequency must not exceed F core /3, and each
ESSI phase must exceed the minimum of 1.5 CLKOUT cycles. The internally sourced
ESSI clock frequency must not exceed F core /4.
7.2.4 Serial Control Signal (SC0)
ESSI0: SC00; ESSI1: SC10
To determine the function of the SC0 signal, select either Synchronous or Asynchronous mode,
according to Table 7-2 . In Asynchronous mode, this signal is used for the receive clock I/O. In
Synchronous mode, this signal is the transmitter data out signal for transmit shift register TX1 or
for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for
addressing in codec systems.
If SC0 is configured as a serial flag signal or receive clock signal, its direction is determined by
the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as
an output, SC0 functions as the serial Output Flag 0 (OF0) or as a receive shift register clock
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
7-3
相关PDF资料
DSPAUDIOEVMMB1E BOARD MOTHER DSP563XX
DSPIC30F2010 DEVELOPMENT KIT KIT DEV EMBEDDED C
DSTRM-KT-0181A DSTREAM DEBUG AND TRACE UNIT
DSUT1CSU SURGE SUPPR NETWORK W/GROUND
DTEL2 SURGE SUPPRESSOR PHONE RJ11/RJ45
DV003001 PROGRAMMER PICSTART PLUS 16C/17C
DV164035 MPLAB ICD3 IN-CIRC DEBUGGER
DV164039 KIT DEV PIC24FJ256DA210
相关代理商/技术参数
DSP56311EVMIG_D 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311EVMIG DSP56311EVM Sample Code
DSP56311EVMUM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Evaluation Module Hardware Reference Manual
DSP56311FACT 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Higher performance programmable DSP for demanding voice and data applications
DSP56311UM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 24-Bit Digital Signal Processor Users Manual
DSP56311UMAD 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Users Manual Addendum
DSP56311VF150 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/300MMACS 150Mhz EFCOP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150B1 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150R2 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT